Integrated circuit memory devices typically require on-chip voltages that are greater in magnitude than voltages supplied thereto from external power supplies (e.g., Vdd). Such on-chip voltages are typically generated using charge pumping circuits. Typical charge pumping circuits are described in U.S. Pat. Nos. 5,706,230 to Lee entitled "Internal Voltage Boosting Method and Circuit For A Semiconductor Memory Device", 5,608,677 to Yoon et al. entitled "Boosting Voltage Circuit Used in Active Cycle of a Semiconductor Memory Device", 5,180,928 to Choi entitled "Constant Voltage Generation of Semiconductor Device, 5,343,088 to Jeon entitled "Charge Pump Circuit for a Substrate Voltage Generator of a Semiconductor Memory Device", 5,266,842 to Park entitled "Charge Pump Circuit for a Substrate Voltage Generator" and 5,315,557 to Kim et al. entitled "Semiconductor Memory Device Having Self-Refresh and Back-Bias Circuitry", assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference. Copending and commonly assigned U.S. application Ser. No. 08/748,189 to Yoon et al. entitled "Voltage Boosting Circuits Having Backup Voltage Boosting Capability", now U.S. Pat. No. 5,796,293, the disclosure of which is hereby incorporated herein by reference, also discloses techniques for boosting voltages in an integrated circuit to levels greater than the magnitude of the power supply voltages applied to the circuit.
A conventional voltage boosting circuit having a voltage level determining circuit therein is also disclosed in U.S. Pat. No. 5,587,956 to Tanida entitled "Semiconductor Memory Device Having Function of Generating Boosted Potential". An improved voltage pumping circuit is also disclosed in U.S. Pat. No. 5,367,489 to Park et al. entitled "Voltage Pumping Circuit For Semiconductor Memory Devices", assigned to the present assignee, the disclosure of which is hereby incorporated herein by reference.
FIG. 1 is a block diagram of a conventional high-voltage generating circuit for a semiconductor device. In FIG. 1, the reference numerals "11" and "12" denote a first charge pumping device and a second charge pumping device, respectively. The first pumping device 11 comprises an oscillator 11A, which operates both in standby and active modes when a control clock signal (e.g., complementary row-address-strobe (RASB)) maintains `high` and `low` logic levels, respectively, and a first charge pumping circuit 11 B. The second charge pumping device 12 comprises an active kicker circuit 12A, which is enabled in the active state when the control clock signal (e.g., RASB) maintains the `low` logic level to produce a pumping signal, and a second charge pumping circuit 12B for pumping charges in accordance with the pumping signal received from the active kicker 12A.
Typically, the pumping efficiency of the first pumping device 11 is maintained relatively low so as to reduce the amount of current consumed during the standby mode, while the pumping efficiency of the second pumping device 12 is maintained relatively high so as to compensate for large currents which may be generated during the active mode of operation. A voltage level detecting section 13 enables the charge pumping circuits 11B and 12B in the first and second pumping devices 11 and 12, so that these circuits can perform charge-pumping operations to maintain high voltage levels (within a predetermined voltage range) if the high voltage (Vpp) detected by the voltage level detecting section 13 becomes lower than a predetermined lower limit threshold. A pre-charging section 14 pre-charges a high-voltage output node for a rapid pumping operation at an initial state. A clamping device 15 prevents the high on-chip voltage Vpp from rising over a predetermined level by "sinking" excessive charges generated during pumping to the supply voltage line if the high voltage Vpp becomes greater than the predetermined level.
The clamping device 15, as shown in detail in FIG. 2, may comprise an NMOS pass transistor N1 and a resistor R1. As will be understood by those skilled in the art, if the high voltage Vpp becomes higher than the sum of the supply voltage Vdd and the threshold voltage Vth between the gate and source of the pass transistor N1, the pass transistor N1 will turn on and form a discharge path through the resistor R1 to the supply voltage line (Vdd). By using this clamping device 15, the high voltage Vpp can typically be maintained at a level which is at or below the sum of the supply voltage Vdd and the gate-source threshold voltage Vth of the pass transistor N1.
Unfortunately, although the NMOS pass transistor N1 may have a significant channel width for providing a low resistance path to the supply line Vdd, the delay associated with discharging an excessively large Vpp may be substantial. Moreover, the period of the external control signal (e.g., RASB) may become too short during high-speed operation and, therefore, the level of the high voltage Vpp may be increased (by the active kicker 12A and the second charge pumping circuit 12B) to an excessive level which may damage devices and isolation regions connected to or adjacent the high voltage Vpp signal line.
Thus, notwithstanding the above described voltage boosting circuits, there continues to be a need for voltage boosting circuits which are less likely to damage devices connected thereto or shorten the lifetime of memory circuits requiring boosted voltage levels.